The following pages link to Sudhakar M. Reddy (Q987742):
Displayed 50 items.
- Thread-parallel integrated test pattern generator utilizing satisfiability analysis (Q987743) (← links)
- A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair (Q3309030) (← links)
- On self-fault diagnosis of the distributed systems (Q3495064) (← links)
- Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits (Q3716977) (← links)
- A New Approach to the Design of Testable PLA's (Q3745777) (← links)
- Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories (Q3877582) (← links)
- A Fault-Tolerant Communication Architecture for Distributed Systems (Q3950485) (← links)
- On the Design of Logic Networks with Redundancy and Testability Considerations (Q4041454) (← links)
- Note on Self-Checking Checkers (Q4044454) (← links)
- Easily Testable Two-Dimensional Cellular Logic Arrays (Q4047454) (← links)
- Further results on decoders for<tex>Q</tex>-ary output channels (Corresp.) (Q4048953) (← links)
- Techniques to Construct (2,1) Separating Systems from Linear Error-Correcting Codes (Q4103011) (← links)
- A Note on Testing Logic Circuits by Transition Counting (Q4119109) (← links)
- (Q4132436) (← links)
- Comments on "Minimal Fault Tests for Combinational Networks" (Q4140872) (← links)
- On Totally Self-Checking Checkers for Separable Codes (Q4149365) (← links)
- A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems (Q4156297) (← links)
- A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines (Q4171989) (← links)
- Delay fault models for VLSI circuits (Q4225360) (← links)
- On fault simulation for synchronous sequential circuits (Q4419650) (← links)
- INCREDYBLE: A new search strategy for design automation problems with applications to testing (Q4419719) (← links)
- Deleting vertices to bound path length (Q4419764) (← links)
- On the role of hardware reset in synchronous sequential circuit test generation (Q4419767) (← links)
- On removing redundancies from synchronous sequential circuits with synchronizing sequences (Q4420906) (← links)
- On the number of tests to detect all path delay faults in combinational logic circuits (Q4420908) (← links)
- A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set (Q4571243) (← links)
- On Minimally Testable Logic Networks (Q4767239) (← links)
- Design of Two-Level Fault-Tolerant Networks (Q5181630) (← links)
- Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions (Q5183411) (← links)
- VERTEX SPLITTING IN DAGS AND APPLICATIONS TO PARTIAL SCAN DESIGNS AND LOSSY CIRCUITS (Q5248984) (← links)
- Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis (Q5280808) (← links)
- On symmetric error correcting and all unidirectional error detecting codes (Q5375444) (← links)
- A decoding algorithm for some convolutional codes constructed from block codes (Q5551982) (← links)
- A note on decoding of block codes (Corresp.) (Q5568909) (← links)
- On decoding iterated codes (Q5595629) (← links)
- A construction for convolutional codes using block codes (Q5607636) (← links)
- A class of high-rate double-error-correcting convolutional codes (Q5630980) (← links)
- Multiple Fault Detection in Combinational Networks (Q5631009) (← links)
- Hybrid block- self-orthogonal convolutional codes (Q5635332) (← links)
- Random error and burst correction by iterated codes (Q5635333) (← links)
- Linear convolutional codes for compound channels (Q5643868) (← links)
- Forward-error correction with decision feedback (Q5650287) (← links)
- New binary codes (Q5655265) (← links)
- Easily Testable Realizations ror Logic Functions (Q5655292) (← links)
- On block codes with specified maximum distance (Corresp.) (Q5657993) (← links)
- Error-Control Techniques for Logic Processors (Q5658002) (← links)
- A Design Procedure for Fault-Locatable Switching Circuits (Q5659450) (← links)
- Fault-Tolerant Asynchronous Networks (Q5672817) (← links)
- Circulant bases for cyclic codes (Corresp.) (Q5682226) (← links)
- Complete Test Sets for Logic Functions (Q5684578) (← links)