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Unidirectional Two Dimensional Systolic Array for Multiplication in GF(2 m ) Using LSB First Algorithm 2009-07-02 Paper More efficient systolic arrays for multiplication...

Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms 2017-07-27 Paper Algorithmic aspects for multiple-choice hardware/software partitioning...

On the hardware implementation of RIPEMD processor: networking high speed hashing, up to 2 Gbps 2006-10-10 Paper 64-bit block ciphers: hardware implementations...

Cryptographic Hardware Based on Programmable CA 2009-01-20 Paper Cellular Automata Architecture for Elliptic Curve Cryptographic Hardware 2009-01-13 Paper...

Paper A systolic array for the regularization of ill-conditioned least-squares problem with triangular Toeplitz matrix 1986-01-01 Paper On systolic array...

Unidirectional Two Dimensional Systolic Array for Multiplication in GF(2 m ) Using LSB First Algorithm 2009-07-02 Paper More efficient systolic arrays for multiplication...

Paper Scalable and modular memory-based systolic architectures for discrete Hartley transform 2017-11-20 Paper Hardware-Efficient Realization of Prime-Length...

Low-Complexity Systolic Karatsuba Multiplier Over $GF(2^{m})$ Based on NIST Polynomials 2021-08-26 Paper Low-Latency High-Throughput Systolic Multipliers...

2013-04-02 Paper Massive black hole binary evolution 2007-03-20 Paper Systolic and hyper-systolic algorithms for the gravitational \(N\)-body problem, with an application...

2022-08-05 Paper Efficient hardware implementations for elliptic curve cryptography over Curve448 2022-07-06 Paper A monolithic hardware implementation of Kyber:...

analysis for factorial data analysis. Part II: Special purpose hardware—the programmable systolic array SARDA 1987-01-01 Paper...

Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation 2018-06-12 Paper Analysis of joint angle-frequency...

Publication Type Efficient systolic multiplications in composite fields for cryptographic systems 2019-08-23 Paper High-Speed Hardware Implementation of Rainbow...

Using Parallel Angle Recoding to Accelerate Rotations 2017-07-27 Paper QCA Systolic Array Design 2017-07-12 Paper FFT Implementation with Fused Floating-Point...

Date of Publication Type Linear systolic multiplier/squarer for fast exponentiation 2016-06-16 Paper Partitioned systolic architecture for modular multiplication...

Publication Date of Publication Type Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime...

Publication Date of Publication Type Survey on hardware implementation of random number generators on FPGA: theory and experimental analyses 2018-03-22...

Date of Publication Type Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic 2017-11-20 Paper https://portal...

Date of Publication Type Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic 2017-11-20 Paper https://portal...

encoder 2023-11-16 Paper Hardware implementation of multiplication over quartic extension fields 2022-10-07 Paper A scalable and systolic architectures of Montgomery...