| Publication | Date of Publication | Type |
|---|
A Fused Floating-Point Four-Term Dot Product Unit
IEEE Transactions on Circuits and Systems I: Regular Papers | 2021-09-02 | Paper |
A Fused Floating-Point Three-Term Adder
IEEE Transactions on Circuits and Systems I: Regular Papers | 2021-08-26 | Paper |
Design and Analysis of Approximate Redundant Binary Multipliers
IEEE Transactions on Computers | 2019-08-13 | Paper |
A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms
IEEE Transactions on Computers | 2018-07-09 | Paper |
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes
IEEE Transactions on Computers | 2018-06-27 | Paper |
A pipelined architecture for the multidimensional DFT
IEEE Transactions on Signal Processing | 2017-09-08 | Paper |
Adder and Multiplier Design in Quantum-Dot Cellular Automata
IEEE Transactions on Computers | 2017-08-08 | Paper |
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations
IEEE Transactions on Computers | 2017-07-27 | Paper |
Priority Tries for IP Address Lookup
IEEE Transactions on Computers | 2017-07-27 | Paper |
A Reduced Complexity Wallace Multiplier Reduction
IEEE Transactions on Computers | 2017-07-27 | Paper |
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division
IEEE Transactions on Computers | 2017-07-27 | Paper |
FFT Implementation with Fused Floating-Point Operations
IEEE Transactions on Computers | 2017-07-12 | Paper |
QCA Systolic Array Design
IEEE Transactions on Computers | 2017-07-12 | Paper |
Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata
IEEE Transactions on Computers | 2017-06-20 | Paper |
A Modified Partial Product Generator for Redundant Binary Multipliers
IEEE Transactions on Computers | 2017-05-16 | Paper |
A 16-bit by 16-bit MAC design using fast 5:3 compressor cells
Journal of VLSI signal processing systems for signal, image and video technology | 2002-12-15 | Paper |
A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications
IEEE Transactions on Signal Processing | 2001-12-02 | Paper |
High-speed CORDIC based on an overlapped architecture and a novel \(\sigma\)-prediction method
Journal of VLSI signal processing systems for signal, image and video technology | 2001-06-21 | Paper |
| scientific article; zbMATH DE number 1067739 (Why is no real title available?) | 1998-11-01 | Paper |
| scientific article; zbMATH DE number 1206079 (Why is no real title available?) | 1998-10-14 | Paper |
Variable-precision, interval arithmetic coprocessors
Reliable Computing | 1997-02-16 | Paper |
| scientific article; zbMATH DE number 903735 (Why is no real title available?) | 1996-10-21 | Paper |
| scientific article; zbMATH DE number 869749 (Why is no real title available?) | 1996-05-29 | Paper |
A software interface and hardware design for variable-precision interval arithmetic
Reliable Computing | 1996-05-27 | Paper |
| scientific article; zbMATH DE number 804626 (Why is no real title available?) | 1995-11-21 | Paper |
Optimal initial approximations for the Newton-Raphson division algorithm
Computing | 1994-12-20 | Paper |
Hardware designs for exactly rounded elementary functions
IEEE Transactions on Computers | 1994-01-01 | Paper |
| scientific article; zbMATH DE number 4010373 (Why is no real title available?) | 1986-01-01 | Paper |
Sign/Logarithm Arithmetic for FFT Implementation
IEEE Transactions on Computers | 1983-01-01 | Paper |
Inner Product Computers
IEEE Transactions on Computers | 1978-01-01 | Paper |
The Sign/Logarithm Number System
IEEE Transactions on Computers | 1975-01-01 | Paper |
| scientific article; zbMATH DE number 3519920 (Why is no real title available?) | 1974-01-01 | Paper |
| scientific article; zbMATH DE number 3420627 (Why is no real title available?) | 1973-01-01 | Paper |
The Quasi-Serial Multiplier
IEEE Transactions on Computers | 1973-01-01 | Paper |
