Pramod Kumar Meher

Available identifiers

zbMath Open meher.pramod-kumarMaRDI QIDQ605723

List of research outcomes

Publication	Date of Publication	Type
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters	2021-09-02	Paper
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over $GF(2^{m})$ Based on NIST Polynomials	2021-08-26	Paper
Comment on “Subquadratic Space-Complexity Digit-Serial Multipliers Over <inline-formula> <tex-math notation="LaTeX">$GF(2^{m})$</tex-math> </inline-formula> Using Generalized <inline-formula> <tex-math notation="LaTeX">$(a, b)$</tex-math> </inline-formula>-Way Karatsuba Algorithm”	2021-08-26	Paper
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition	2021-08-26	Paper
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications	2021-08-26	Paper
Low-Latency High-Throughput Systolic Multipliers Over <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> for NIST Recommended Pentanomials	2021-08-26	Paper
Subquadratic Space-Complexity Digit-Serial Multipliers Over <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> Using Generalized <formula formulatype="inline"><tex Notation="TeX">$(a,b)$</tex></formula>-Way Karatsuba Algorithm	2021-08-26	Paper
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach	2021-08-26	Paper
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications	2021-08-26	Paper
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data	2021-08-26	Paper
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> Using Symmetric TMVP and Block Recombination Techniques	2021-08-26	Paper
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation	2021-08-26	Paper
50 Years of CORDIC: Algorithms, Architectures, and Applications	2021-08-26	Paper
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm	2018-08-22	Paper
Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT	2018-07-18	Paper
Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames	2018-07-18	Paper
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic	2018-06-27	Paper
Scalable and modular memory-based systolic architectures for discrete Hartley transform	2017-11-20	Paper
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic	2017-07-12	Paper
High-speed \(\mathrm{RS}(255, 239)\) decoder based on LCC decoding	2012-04-04	Paper
Efficient bit-parallel multipliers over finite fields GF\((2^m)\)	2010-11-25	Paper
Systolic VLSI and FPGA Realization of Artificial Neural Networks	2010-09-24	Paper
Nonlinear channel equalization for wireless communication systems using Legendre neural networks	2009-09-01	Paper
WMicaD: A new digital watermarking technique using independent component analysis	2008-08-28	Paper
https://portal.mardi4nfdi.de/entity/Q4414584	2003-07-25	Paper

Research outcomes over time

This page was built for person: Pramod Kumar Meher