Systolic VLSI and FPGA Realization of Artificial Neural Networks

DOI10.1007/978-3-642-12775-5_15zbMATH Open1202.68082OpenAlexW59985614MaRDI QIDQ4929795FDOQ4929795

Authors: Pramod Kumar Meher 

Publication date: 24 September 2010

Published in: Computational Intelligence in Optimization (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-12775-5_15

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zbMATH Keywords

systolic arraysVLSI structures

Mathematics Subject Classification ID

Learning and adaptive systems in artificial intelligence (68T05) Computer system organization (68M99)

Cited In (5)

• FPGA realization of fractional order neuron
• Building an artificial brain using an FPGA based CAM-brain machine
• Title not available (Why is that?)
• Title not available (Why is that?)
• Neural Networks and Systolic Array Design

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