Using a standard clock technique for efficient simulation (Q1183385)

An efficient simulation technique for the parametric study of discrete- event dynamic systems (DEDS), called the standard clock technique, is introduced and its properties studied. The measure of efficiency used is the computational effort necessary to obtain specific results. Sample paths of a DEDS under a finite number of distinct parameter values are generated simultaneously; one clock mechanism (standard clock) that determines the type and time of event is shared between all sample paths. This technique eliminates a considerable amount of duplications of random variate generation, generation of the next event type and time, and in some cases updating the state of the system. Two factors contribute to the reduction of simulation work when the standard clock is used: the simplicity of the clock mechanism, and the sharing of information between many sample paths. To determine the next event time and type, no event list search is needed; one uniform random number generation, one comparison and at most two memory references are sufficient. Compared to conventional simulation methods, however, the standard clock technique introduces more randomness into the simulation and hence the estimators generally have larger variance. An application to queuing networks is presented.