Scenario-based verification of real-time systems using UPPAAL

DOI10.1007/S10703-010-0103-ZzbMath1209.68323OpenAlexW2146580567MaRDI QIDQ633291

Sandie Balaguer, Shuhao Li, Saulius Pusinskas, Brian Nielsen, Alexandre David, Kim Guldstrand Larsen

Publication date: 31 March 2011

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10703-010-0103-z

zbMATH Keywords

verificationmodelingtimed automatareal-time systemscenariolive sequence chart

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (2)

Scenario-based verification of real-time systems using UPPAAL ⋮ SMT-based scenario verification for hybrid systems

Uses Software

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• Uppaal

Cites Work

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• Scenario-based verification of real-time systems using UPPAAL
• A theory of timed automata
• Real-time system = discrete system + clock variables
• Kronos: A verification tool for real-time systems
• The computational complexity of scenario-based agent verification and design
• Schedulability of asynchronous real-time concurrent objects
• SYNTHESIZING STATE-BASED OBJECT SYSTEMS FROM LSC SPECIFICATIONS
• On the Expressive Power of Live Sequence Charts
• Foundations of Software Science and Computation Structures
• Formal Methods for the Design of Real-Time Systems
• Tools and Algorithms for the Construction and Analysis of Systems
• Check It Out: On the Efficient Formal Verification of Live Sequence Charts
• LSCs: Breathing life into message sequence charts
• Verification of a radio-based signaling system using the STATEMATE verification environment

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