Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs
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Publication:3172988
DOI10.1007/978-3-642-23951-9_32zbMath1285.94068OpenAlexW154446972MaRDI QIDQ3172988
Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol
Publication date: 7 October 2011
Published in: Cryptographic Hardware and Embedded Systems – CHES 2011 (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-642-23951-9_32
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