The Complexity of Fault Detection Problems for Combinational Logic Circuits

DOI10.1109/TC.1982.1676041zbMath0484.94039MaRDI QIDQ3944512

Shunichi Toida, Hideo Fujiwara

Publication date: 1982

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

zbMATH Keywords

polynomial algorithmstest generationcombinational circuitsdesign for testability

Mathematics Subject Classification ID

Related Items (4)

Fault detection and pinning control of Boolean networks ⋮ Boolean derivative calculation with application to fault detection of combinational circuits via the semi-tensor product method ⋮ Computations over finite monoids and their test complexity ⋮ Efficient VLSI fault simulation

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