Bounded Depth Circuits with Weighted Symmetric Gates: Satisfiability, Lower Bounds and Compression

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Publication:4608645

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DOI10.4230/LIPIcs.MFCS.2016.82zbMath1398.68259OpenAlexW2540343126MaRDI QIDQ4608645

Junichi Teruyama, Kazuhisa Seto, Takayuki Sakai, Suguru Tamaki

Publication date: 21 March 2018

Full work available at URL: http://drops.dagstuhl.de/opus/volltexte/2016/6490/

zbMATH Keywords

circuit complexity maximum satisfiability exponential time algorithm circuit minimization

Mathematics Subject Classification ID

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Related Items (6)

Unnamed Item ⋮ Unnamed Item ⋮ Gate elimination: circuit size lower bounds and \#SAT upper bounds ⋮ Unnamed Item ⋮ Bounded depth circuits with weighted symmetric gates: satisfiability, lower bounds and compression ⋮ A \#SAT algorithm for small constant-depth circuits with PTF gates

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