Improved Design of High-Performance Parallel Decimal Multipliers

DOI10.1109/TC.2009.167zbMath1367.65253OpenAlexW2133140834WikidataQ60350141 ScholiaQ60350141MaRDI QIDQ5280770

P. Montuschi, Álvaro Vázquez, Elisardo Antelo

Publication date: 27 July 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2009.167

Mathematics Subject Classification ID

Parallel numerical computation (65Y05) Numerical algorithms for computer arithmetic, etc. (65Y04)

Related Items (1)

Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers

This page was built for publication: Improved Design of High-Performance Parallel Decimal Multipliers