A design of time-optimum and register-number-minimum systolic convolvers (Q582105)
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English | A design of time-optimum and register-number-minimum systolic convolvers |
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A design of time-optimum and register-number-minimum systolic convolvers (English)
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1989
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We present an optimum bit-parallel/world-sequential systolic convolver. Our design is the best one among the previous many convolvers in the sense that its optimality in time and space performances is simultaneously attained without augmenting any global control, broadcasting, initial-data-preloading, and/or multi-sequential or parallel I/O ports which were allowed in most of the previous designs. As an application of our convolver we give a systolic polynomial divider which can compute the polynomial division in exactly \(n+O(1)\) optimum steps on \([\min (n-m,m)/2]+O(1)\) systolic cells for the devition of any degree n polynomial by any degree m polynomial (n\(\geq m)\).
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VLSI design
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real-time pattern matcher
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systolic array
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systolic algorithm
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systolic convolver
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polynomial divider
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