A compact DSP core with static floating-point arithmetic (Q2432118)

From MaRDI portal
Revision as of 21:05, 24 June 2024 by ReferenceBot (talk | contribs) (‎Changed an Item)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
scientific article
Language Label Description Also known as
English
A compact DSP core with static floating-point arithmetic
scientific article

    Statements

    title
    A compact DSP core with static floating-point arithmetic (English)
    0 references
    author
    Tay-Jyi Lin
    0 references
    Hung-Yueh Lin
    0 references
    Chie-Min Chao
    0 references
    Chih-Wei Liu
    0 references
    Chih-Wei Jen
    0 references
    publication date
    25 October 2006
    0 references
    zbMATH Keywords
    signal processing
    0 references

    Identifiers

    zbMATH DE Number
    5067078
    0 references
    OpenAlex ID
    W2170840568
    0 references
     
    Retrieved from "https://portal.mardi4nfdi.de/w/index.php?title=Item:Q2432118&oldid=34893282"
    Powered by MediaWiki