Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers (Q2676842)

From MaRDI portal
Revision as of 05:34, 30 July 2024 by ReferenceBot (talk | contribs) (‎Changed an Item)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
scientific article
Language Label Description Also known as
English
Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers
scientific article

    Statements

    Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers (English)
    0 references
    0 references
    0 references
    28 September 2022
    0 references
    parallel multiplier
    0 references
    radix-4
    0 references
    Booth encoding scheme
    0 references
    Booth algorithm
    0 references
    high-speed
    0 references
    pass-transistor logic
    0 references

    Identifiers