An Architecture for Bitonic Sorting with Optimal VLSI Performnance (Q3323284)

From MaRDI portal
Revision as of 11:10, 30 July 2024 by Openalex240730090724 (talk | contribs) (Set OpenAlex properties.)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
scientific article
Language Label Description Also known as
English
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
scientific article

    Statements

    An Architecture for Bitonic Sorting with Optimal VLSI Performnance (English)
    0 references
    0 references
    0 references
    1984
    0 references
    area-time tradeoff
    0 references
    optimal algorithms
    0 references
    parallel computation
    0 references
    VLSI complexity
    0 references
    interconnection network
    0 references
    pleated cube-connected cycles
    0 references
    stable bitonic sorting
    0 references

    Identifiers

    0 references
    0 references
    0 references
    0 references
    0 references