Hardware reduction for LUT-based Mealy FSMs (Q1797893)

From MaRDI portal
Revision as of 09:25, 16 December 2024 by Import241208061232 (talk | contribs) (Normalize DOI.)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
scientific article
Language Label Description Also known as
English
Hardware reduction for LUT-based Mealy FSMs
scientific article

    Statements

    title
    Hardware reduction for LUT-based Mealy FSMs (English)
    0 references
    author
    Larysa Titarenko
    0 references
    Kamil Mielcarek
    0 references
    Alexander Barkalov
    0 references
    publication date
    22 October 2018
    0 references
    zbMATH Keywords
    Mealy FSM
    0 references
    synthesis
    0 references
    FPGA
    0 references
    LUT
    0 references
    partition
    0 references
    encoding collections of output variables
    0 references

    Identifiers

    zbMATH DE Number
    6960404
    0 references
    OpenAlex ID
    W2894724188
    0 references
     
    Retrieved from "https://portal.mardi4nfdi.de/w/index.php?title=Item:Q1797893&oldid=38756373"
    Powered by MediaWiki