Hardware reduction for LUT-based Mealy FSMs
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Publication:1797893
DOI10.2478/AMCS-2018-0046zbMath1485.68015OpenAlexW2894724188MaRDI QIDQ1797893
Kamil Mielcarek, Larysa Titarenko, Alexander Barkalov
Publication date: 22 October 2018
Published in: International Journal of Applied Mathematics and Computer Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.2478/amcs-2018-0046
Related Items (5)
Twofold state assignment for the Moore finite state machines ⋮ Improving characteristics of LUT-based Mealy FSMs ⋮ Optimization of CMCU with code sharing ⋮ Improving the LUT count for mealy FSMS with transformation of output collections ⋮ Analysis of safeness in a Petri net-based specification of the control part of cyber-physical systems
Cites Work
- Structural decomposition as a tool for the optimization of an FPGA-based implementation of a Mealy FSM
- Logic synthesis for compositional microprogram control units
- Finite state machine logic synthesis for complex programmable logic devices
- Minimum energy control of descriptor fractional discrete-time linear systems with two different fractional orders
- 5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs
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