The following pages link to Computer Aided Verification (Q5900667):
Displayed 12 items.
- A multiple-valued logic approach to the design and verification of hardware circuits (Q266875) (← links)
- Automated verification and refinement for physical-layer protocols (Q539420) (← links)
- Verification of consensus algorithms using satisfiability solving (Q658669) (← links)
- Latticed \(k\)-induction with an application to probabilistic programs (Q832288) (← links)
- Property-directed incremental invariant generation (Q939166) (← links)
- Backward symbolic execution with loop folding (Q2145317) (← links)
- SMT-based scenario verification for hybrid systems (Q2441772) (← links)
- Bounded Model Checking with Parametric Data Structures (Q2864380) (← links)
- SAT-Based Model Checking without Unrolling (Q3075471) (← links)
- Exact Incremental Analysis of Timed Automata with an SMT-Solver (Q3172851) (← links)
- Satisfiability Modulo Theories (Q3176369) (← links)
- Theorem Proving Based on Proof Scores for Rewrite Theory Specifications of OTSs (Q5403086) (← links)