A multiple-valued logic approach to the design and verification of hardware circuits (Q266875)
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scientific article; zbMATH DE number 6566310
| Language | Label | Description | Also known as |
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| English | A multiple-valued logic approach to the design and verification of hardware circuits |
scientific article; zbMATH DE number 6566310 |
Statements
A multiple-valued logic approach to the design and verification of hardware circuits (English)
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7 April 2016
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multiple-valued logic
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hardware verification
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hardware simulation
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verification complexity
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De Morgan canonical form
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0.91276145
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0.89710295
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