δ-Bit serial binary addition with linear threshold networks

DOI10.1007/BF00929619MaRDI QIDQ3125434zbMATH OpenFDO

Authors Sorin Dan Cotofana, Stamatis Vassiliadis

Publication date 18 March 1997

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BF00929619

zbMATH Keywords

feed-forward networkthreshold gates

Mathematics Subject Classification ID

Computer system organization (68M99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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(3)

• 2-1 addition and related arithmetic operations with threshold logic
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• Two operand binary adders with threshold logic

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