A Reduced Complexity Wallace Multiplier Reduction

DOI10.1109/TC.2010.103MaRDI QIDQ5280728zbMATH OpenFDO

Authors Ron S. Waters, Earl E. jun. Swartzlander

Publication date 27 July 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2010.103

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04)

Cited in

(3)

• A novel parallel prefix adder for optimized radix-2 FFT processor
• Digital equalization for cancellation of noise-like interferences in adaptive spatial filtering
• Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers

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