A Versatile Reconfigurable Bit-Serial Multiplier Architecture in Finite Fields GF(2m)

DOI10.1007/978-3-540-89985-3_28MaRDI QIDQ3628444zbMATH OpenOpenAlexFDO

Authors Morteza Nikooghadam, Ehsan Malekian, Ali Zakerolhosseini

Publication date 20 May 2009

Published in Communications in Computer and Information Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-540-89985-3_28

zbMATH Keywords

bit-serial multiplierelliptic curve cryptographyGalois fieldirreducible polynomiallinear feedback shift register

Mathematics Subject Classification ID

Computer system organization (68M99)

Recommendations

• scientific article; zbMATH DE number 1997929
• scientific article; zbMATH DE number 1878334
• A new architecture for a parallel finite field multiplier with low complexity based on composite fields
• Bit-parallel arithmetic implementations over finite fields \(\text{GF}(2^m)\) with reconfigurable hardware
• A novel approach for bit-serial \(AB^{2}\) multiplication in finite fields \(\mathrm{GF}(2^m)\)

Cites work

• AOP arithmetic architectures over GF(2\(^m\))
• Elliptic Curve Cryptosystems
• scientific article; zbMATH DE number 954401 (Why is no real title available?)
• scientific article; zbMATH DE number 6433928 (Why is no real title available?)
• Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields
• Structure of parallel multipliers for a class of fields GF(2^ m)

Cited in

(8)

• Bit-parallel arithmetic implementations over finite fields \(\text{GF}(2^m)\) with reconfigurable hardware
• A novel approach for bit-serial \(AB^{2}\) multiplication in finite fields \(\mathrm{GF}(2^m)\)
• Combining multiplication methods with optimized processing sequence for polynomial multiplier in \(\mathrm{GF}(2^k)\)
• Reconfigurable design of Galois field multiplication in symmetric cryptography
• scientific article; zbMATH DE number 1941155 (Why is no real title available?)
• A formal approach to designing multiple-valued arithmetic circuits
• A VLSI design for computing exponentiations in GF(2/sup m/) and its application to generate pseudorandom number sequences
• A new bit-serial multiplier over GF(pm) using irreducible trinomials

This page was built for publication: A Versatile Reconfigurable Bit-Serial Multiplier Architecture in Finite Fields GF(2m)

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3628444)