scientific article; zbMATH DE number 1997929

MaRDI QIDQ4432867zbMATH OpenFDO

Authors Chang Nian Zhang, Hua Li

Publication date 29 October 2003

zbMATH Keywords

VLSI architecture

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Recommendations

• VLSI algorithms, architectures, and implementation of a versatile GF(2/sup m/) processor
• VLSI Architectures for Computing Multiplications and Inverses in GF(2^m)
• scientific article; zbMATH DE number 1941155
• A new hardware architecture for operations in GF(2/sup n/)
• scientific article; zbMATH DE number 4102996
• Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ )
• Bit-parallel arithmetic implementations over finite fields \(\text{GF}(2^m)\) with reconfigurable hardware
• scientific article; zbMATH DE number 1258204

Cited in

(5)

• VLSI algorithms, architectures, and implementation of a versatile GF(2/sup m/) processor
• A Versatile Reconfigurable Bit-Serial Multiplier Architecture in Finite Fields GF(2m)
• VLSI Architectures for Computing Multiplications and Inverses in GF(2^m)
• scientific article; zbMATH DE number 1504816 (Why is no real title available?)
• A VLSI design for computing exponentiations in GF(2/sup m/) and its application to generate pseudorandom number sequences

This page was built for publication:

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4432867)