A compact layout for the three-dimensional tree of meshes

DOI10.1016/0893-9659(88)90066-3MaRDI QIDQ1105621zbMATH OpenOpenAlexFDO

Authors Ronald I. Greenberg, Charles E. Leiserson

Publication date 1988

Published in Applied Mathematics Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0893-9659(88)90066-3

zbMATH Keywords

embeddingtree of meshes graphVLSI graph layout

Mathematics Subject Classification ID

Graph theory (05C99)

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Cites work

• scientific article; zbMATH DE number 3876584 (Why is no real title available?)
• A framework for solving VLSI graph layout problems
• New lower bound techniques for VLSI
• Three-Dimensional Circuit Layouts
• Universality considerations in VLSI circuits

Cited in

(4)

• On meshy trees
• UNIVERSAL ROUTING AND PERFORMANCE ASSURANCE FOR DISTRIBUTED NETWORKS
• scientific article; zbMATH DE number 3943048 (Why is no real title available?)
• An alternative mapping of 3-D space onto processor arrays

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