Three-Dimensional Circuit Layouts

DOI10.1137/0215057MaRDI QIDQ3753506zbMATH OpenOpenAlexFDO

Authors Arnold L. Rosenberg, F. Thomson Leighton

Publication date 1986

Published in SIAM Journal on Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1137/0215057

zbMATH Keywords

graph embeddingsVLSIgraph layoutsarea-volume tradeoffsmultilayer circuit realizationsone-active layer layouts

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Graph theory (including graph drawing) in computer science (68R10) Applications of graph theory to circuits and networks (94C15) Graph theory (05C99)

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• Communication-efficient parallel algorithms for distributed random-access machines
• A compact layout for the three-dimensional tree of meshes
• Routing vertex disjoint Steiner-trees in a cubic grid and connections to VLSI
• 3D integrated circuits layout optimization game
• Optimal three-dimensional layout of interconnection networks
• Optimal placement of UV-based communications relay nodes
• Clutters and circuits. III
• Planar acyclic computation
• Complexities of layouts in three-dimensional VLSI circuits
• Upward three-dimensional grid drawings of graphs
• Optimal three-dimensional layouts of complete binary trees
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• scientific article; zbMATH DE number 3940771 (Why is no real title available?)
• Routing in a three-dimensional chip
• Representations of graphs and networks (coding, layouts and embeddings)

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