Three-Dimensional Integrated Circuit Layout

DOI10.1017/CBO9780511666384MaRDI QIDQ4001865zbMATH OpenOpenAlexWikidataFDO

Authors Andrew C. Harter

Publication date 23 January 1993

Full work available at URL https://doi.org/10.1017/cbo9780511666384

zbMATH Keywords

three-dimensional integrated circuitstopology of circuit layout

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to computer science (68-02) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Circuits, networks (94C99)

Recommendations

• Three-Dimensional Circuit Layouts
• VLSI design in the 3rd dimension
• scientific article; zbMATH DE number 3845502
• Three-Dimensional VLSI
• Routing in a three-dimensional chip

Cited in

(9)

• Low-degree minimum spanning trees
• Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
• scientific article; zbMATH DE number 434571 (Why is no real title available?)
• scientific article; zbMATH DE number 5657967 (Why is no real title available?)
• Three-Dimensional Circuit Layouts
• VLSI design in the 3rd dimension
• Optimal three-dimensional VLSI layouts
• scientific article; zbMATH DE number 2119932 (Why is no real title available?)
• 3D integrated circuits layout optimization game

This page was built for publication: Three-Dimensional Integrated Circuit Layout

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4001865)