Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

DOI10.1016/J.JCSS.2012.09.005MaRDI QIDQ1953829zbMATH OpenOpenAlexFDO

Authors Masoumeh Ebrahimi, Masoud Daneshtalab, P. Liljeberg, J. Plosila, Hannu Tenhunen

Publication date 11 June 2013

Published in Journal of Computer and System Sciences (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.jcss.2012.09.005

zbMATH Keywords

businter-layer communicationnetwork topologythree-dimensional Networks-on-Chip

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

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(4)

• Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
• Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
• A fuzzy-based routing scheme for network-on-chip with honeycomb topology
• Computing the Optimal Longest Queue Length in Torus Networks

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