Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels

DOI10.1016/J.JCSS.2012.09.004MaRDI QIDQ1953823zbMATH OpenOpenAlexFDO

Authors Amir-Mohammad Rahmani, P. Liljeberg, J. Plosila, Hannu Tenhunen

Publication date 11 June 2013

Published in Journal of Computer and System Sciences (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.jcss.2012.09.004

zbMATH Keywords

3D Networks-on-Chipbidirectional bisynchronous vertical channelsforecasting-based dynamic power management

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Recommendations

• Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
• Designing reliable and efficient networks on chips
• Networks-on-Chips
• Reliable energy-aware application mapping and voltage-frequency island partitioning for GALS-based NoC
• A high level power model for network-on-chip (NoC) router

Cited in

(2)

• Reliable energy-aware application mapping and voltage-frequency island partitioning for GALS-based NoC
• Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

This page was built for publication: Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1953823)