A design of Reed-Solomon decoder with systolic-array structure

DOI10.1109/12.368005MaRDI QIDQ4419610zbMATH OpenOpenAlexFDO

Authors Keiichi Iwamura, Yasunori Dohi, Hideki Imai

Publication date 1995

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.368005

zbMATH Keywords

high-speed processingVLSI implementation

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cited in

(5)

• A novel low-cost multi-mode Reed Solomon decoder design based on Peterson-Gorenstein-Zierler algorithm
• VLSI architecture of modified Euclidean algorithm for Reed-Solomon code.
• A systolic Reed-Solomon encoder
• Systolic Array Architecture Implementing Berlekamp–Massey–Sakata Algorithm for Decoding Codes on a Class of Algebraic Curves
• A systolic array architecture for fast decoding of one-point AG codes and scheduling of parallel processing on it

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