A graph-theoretic via minimization algorithm for two-layer printed circuit boards

DOI10.1109/TCS.1983.1085357MaRDI QIDQ4742710zbMATH OpenFDO

Authors Ray Ruen-Wu Chen, Yoji Kajitani, Shu Park Chan

Publication date 1983

Published in IEEE Transactions on Circuits and Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TCS.1983.1085357

zbMATH Keywords

polynomial timepreassignment of line segments

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15)

Cited in

(16)

• Edges and switches, tunnels and bridges
• An algorithm for min-cost edge-disjoint cycles and its applications
• A characterization of signed hypergraphs and its applications to VLSI via minimization and logic synthesis
• An approximate max-flow min-cut relation for undirected multicommodity flow, with applications
• Orthogonal drawings of graphs for the automation of VLSI circuit design
• Polyhedral results for the bipartite induced subgraph problem
• A projected gradient algorithm for solving the maxcut SDP relaxation
• Maximum weighted induced bipartite subgraphs and acyclic subgraphs of planar cubic graphs
• Feasible direction algorithm for solving the SDP relaxations of quadratic {−1, 1} programming problems
• Solving VLSI design and DNA sequencing problems using bipartization of graphs
• Randomized heuristics for the Max-Cut problem
• The genus of regular languages
• A multiple search operator heuristic for the max-k-cut problem
• Greedy randomized adaptive search procedures with path relinking. An analytical review of designs and implementations
• On 1-skeleton of the cut polytopes
• Mathematical methods for physical layout of printed circuit boards: an overview

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