A hardware approach to value function iteration

DOI10.1016/J.JEDC.2020.103894MaRDI QIDQ2191461zbMATH OpenOpenAlexFDO

Authors Alessandro Peri

Publication date 25 June 2020

Published in Journal of Economic Dynamics and Control (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.jedc.2020.103894

zbMATH Keywords

business cyclesdynamic programmingFPGAgrowth modelpipelining

Mathematics Subject Classification ID

Game theory, economics, finance, and other social and behavioral sciences (91-XX)

Recommendations

• Tapping the supercomputer under your desk: solving dynamic equilibrium models with graphics processors
• Approximate dynamic programming with post-decision states as a solution method for dynamic economic models
• High-dimensional dynamic stochastic model representation
• Solving nonlinear dynamic stochastic models: an algorithm computing value function by simulations
• Benchmarking machine-learning software and hardware for quantitative economics

Cites work

• Benchmarking machine-learning software and hardware for quantitative economics
• Comparing solution methods for dynamic equilibrium economies
• scientific article; zbMATH DE number 3126094 (Why is no real title available?)
• scientific article; zbMATH DE number 52448 (Why is no real title available?)
• Precautionary savings, illiquid assets, and the aggregate consequences of shocks to household income risk
• Risk measures on \(\mathcal{P}(\mathbb R)\) and value at risk with probability/loss function
• Tapping the supercomputer under your desk: solving dynamic equilibrium models with graphics processors

Cited in

(2)

• Tapping the supercomputer under your desk: solving dynamic equilibrium models with graphics processors
• Programming FPGAs for economics: an introduction to electrical engineering economics

This page was built for publication: A hardware approach to value function iteration

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2191461)