A mixed-mode BIST scheme based on folding compression

DOI10.1007/BF02962213MaRDI QIDQ1613249zbMATH OpenOpenAlexFDO

Authors Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich

Publication date 28 August 2002

Published in Journal of Computer Science and Technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf02962213

zbMATH Keywords

mixed mode scan-based BISTrandom pattern testing

Mathematics Subject Classification ID

Pattern recognition, speech recognition (68T10)

Recommendations

• Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
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• Single-reference multiple intermediate signature (SREMIS) analysis for BIST

Cites work

• A Greedy Heuristic for the Set-Covering Problem
• Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

Cited in

(3)

• Two level core test compression based on partial test vector reuse and VRL coding
• Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
• A scheme of test data compression based on coding of even bits marking and selective output inversion

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