Arithmetic additive generators of pseudo-exhaustive test patterns

DOI10.1109/12.536236MaRDI QIDQ4420868zbMATH OpenOpenAlexFDO

Authors Sanjay Gupta, Janusz Rajski, Jerzy Tyszer

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.536236

zbMATH Keywords

accumulatorsarithmetic generatorsbuilt-in self-testdata-path architecturespseudo-exhaustive generatorsstate coverage

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Reliability, testing and fault tolerance of networks and computer systems (68M15)

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Cited in

(6)

• A mixed-mode BIST scheme based on folding compression
• Pseudorandom test pattern generators for built-in self-testing: a power reduction method
• Verification Testing—A Pseudoexhaustive Test Technique
• Exhaustive test pattern generation using cyclic codes
• Programmable BIST space compactors
• Universal Address Sequence Generator for Memory Built-in Self-test*

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