Pseudorandom test pattern generators for built-in self-testing: a power reduction method

DOI10.1023/B:AURC.0000038729.41847.F0zbMATH Open1079.68511OpenAlexW2001429498MaRDI QIDQ2487656FDOQ2487656

Authors: I. A. Murashko, Vyacheslav Yarmolik 

Publication date: 8 August 2005

Published in: Automation and Remote Control (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/b:aurc.0000038729.41847.f0

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Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

Cited In (2)

• Arithmetic additive generators of pseudo-exhaustive test patterns
• Synthesis of pseudorandom test pattern generators

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