A non-iterative gate resizing algorithm for high reduction in power consumption

DOI10.1016/S0167-9260(97)00024-2MaRDI QIDQ3840912zbMATH OpenFDO

Authors

Publication date 13 August 1998

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S0167-9260(97)00024-2

zbMATH Keywords

gate resizinglow powerlow-power optimization

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cited in

(3)

• Modeling leakage power reduction in VLSI as optimization problems
• scientific article; zbMATH DE number 1690165 (Why is no real title available?)
• GATE RESIZING TO REDUCE POWER CONSUMPTION

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