Access and Alignment of Data in an Array Processor
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(32)- Efficient algorithms and methods to solve dynamic MINs stability problem using stable matching with complete ties
- A unified theory of interconnection network structure
- Self-routing control algorithms and the passability of random inputs by the base-line network
- Independent connections: An easy characterization of baseline-equivalent multistage interconnection networks
- A graph theoretical approach to equivalence of multistage interconnection networks
- A layout for the shuffle-exchange network with theta(N^ 2 /log N) area
- An implementation of a nonlinear skewing scheme
- Perfect Latin squares
- A general performance analysis method for uniform memory architectures
- Performance analysis of augmented partitioned multistage interconnection networks
- Parallel access by butterfly networks for any degree permutation polynomial and ARP interleavers
- A mathematical abstraction of the rearrangeability conjecture for shuffle-exchange networks
- Permuting data with the Omega network
- Strict-sense nonblocking conditions for the \(\log_2 N - 1\) multirate switching fabric for the discrete bandwidth model
- Analyzing permutation capability of multistage interconnection networks with colored Petri nets
- The vector multiprocessor
- The computation and communication complexity of a parallel banded system solver
- A method of batching conflict routings in shuffle-exchange networks
- Universality of iterated networks
- The half cleaner lemma: constructing efficient interconnection networks from sorting networks
- A theory of decomposition into prime factors of layered interconnection networks
- Systolic arrays for multidimensional discrete transforms
- Rotator design
- A d-move local permutation routing for the d-cube
- Parallel stereocorrelation on a reconfigurable multi-ring network.
- The generalized 3-connectivity of a family of regular networks
- A methodology for designing, modifying, and implementing Fourier transform algorithms on various architectures
- Bounds on evacuation time for deflection routing
- A generalization of the perfect shuffle
- Efficient address generation in a parallel processor
- A reliable and fault-tolerant interconnection network
- All-to-all personalized exchange in generalized shuffle-exchange networks
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