Efficient address generation in a parallel processor

DOI10.1016/0020-0190(90)90078-CMaRDI QIDQ917271zbMATH OpenOpenAlexFDO

Authors De-Lei Lee

Publication date 1990

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0020-0190(90)90078-c

zbMATH Keywords

memory address generationparallel memory systemparallel processor

Mathematics Subject Classification ID

Computer system organization (68M99) Analysis of algorithms and problem complexity (68Q25)

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Cites work

• Access and Alignment of Data in an Array Processor
• The Organization and Use of Parallel Memories
• Theoretical Limitations on the Efficient Use of Parallel Memories

Cited in

(4)

• Running ASCEND, DESCEND and PIPELINE algorithms in parallel using small processors
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