Efficient address generation in a parallel processor

DOI10.1016/0020-0190(90)90078-CMaRDI QIDQ917271zbMATH OpenOpenAlexFDO

Authors De-Lei Lee

Publication date 1990

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0020-0190(90)90078-c

zbMATH Keywords

parallel processormemory address generationparallel memory system

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Computer system organization (68M99)

Recommendations

• Efficient address generation for affine subscripts in data-parallel programs
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Cites work

• Access and Alignment of Data in an Array Processor
• The Organization and Use of Parallel Memories
• Theoretical Limitations on the Efficient Use of Parallel Memories

Cited in

(3)

• scientific article; zbMATH DE number 1953333 (Why is no real title available?)
• Running ASCEND, DESCEND and PIPELINE algorithms in parallel using small processors
• scientific article; zbMATH DE number 3974298 (Why is no real title available?)

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