Accurate and Efficient Estimation of Logic Circuits Reliability Bounds

DOI10.1109/TC.2014.2315633MaRDI QIDQ2982258zbMATH OpenFDO

Authors Walid Ibrahim, Marwa Shousha, John W. Chinneck

Publication date 16 May 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2014.2315633

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cited in

(6)

• Computation of contact-circuit reliability
• Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates
• scientific article; zbMATH DE number 7346395 (Why is no real title available?)
• Flexible reliability assessment of digital circuits based on signal probability
• Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs
• New Metrics for the Reliability of Approximate and Probabilistic Adders

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