An approach to decrease dimensions of field-effect transistors without p-n-junctions
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An approach to decrease dimensions of field-effect transistors without \(p-n\)-junctions
Recommendations
- DECREASING OF SPATIAL DIMENSION OF A SERIAL OF DIFFUSED-JUNCTION RECTIFIERS IN A MULTILAYER STRUCTURE IN ACCOUNT WITH NONLINEAR EFFECTS: OPTIMIZATION OF ANNEALING TIME
- Optimization of manufacturing of emitter-coupled logic to decrease surface of chip
- Optimization of diffusion process for production of systems of diffused-junction rectifiers
- An individual particle approach to noise in pseudomorphic heterojunction field effect transistors
- Influence of porosity of materials on redistribution of dopant during manufacturing of diffusion-junction rectifiers in semiconductor heterostructures
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