Optimization of manufacturing of emitter-coupled logic to decrease surface of chip

DOI10.1142/S021797921550023XMaRDI QIDQ5249436zbMATH OpenFDO

Authors E. L. Pankratov, E. A. Bulaeva

Publication date 6 May 2015

Published in International Journal of Modern Physics B (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1142/S021797921550023X

zbMATH Keywords

decreasing surface of chipemitter-coupled logicoptimization of technological process

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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Cites work

• A Jastrow correlation factor for two-dimensional parabolic quantum dots
• scientific article; zbMATH DE number 3046362 (Why is no real title available?)

Cited in

(1)

• An approach to decrease dimensions of field-effect transistors without p-n-junctions

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