Area-time optimal VLSI networks for multiplying matrices

DOI10.1016/0020-0190(80)90006-XMaRDI QIDQ1145672zbMATH OpenOpenAlexFDO

Authors Jean E. Vuillemin, F. P. Preparata

Publication date 1980

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0020-0190(80)90006-x

zbMATH Keywords

matrix multiplicationarea-time complexityoptimal VLSI networks

Mathematics Subject Classification ID

Numerical linear algebra (65F99) Analysis of algorithms and problem complexity (68Q25)

Cites work

• The Area-Time Complexity of Binary Multiplication

Cited in

(8)

• The matrix equation MX + XN = B in the VLSI model
• An O(1) time optimal algorithm for multiplying matrices on reconfigurable mesh
• Area-time tradeoffs for matrix multiplication and related problems in VLSI models
• On the VLSI complexity of some arithmetic and numerical problems
• The performance of multilective VLSI algorithms
• Area-period tradeoffs for multiplication of rectangular matrices
• Area-time tradeoff for rectangular matrix multiplication in VLSI models
• New lower bound techniques for VLSI

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