The Area-Time Complexity of Binary Multiplication

From MaRDI portal
Publication:3912011

DOI10.1145/322261.322269zbMath0462.68014OpenAlexW2165495918MaRDI QIDQ3912011

H. T. Kung, Richard P. Brent

Publication date: 1981

Published in: Journal of the ACM (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1145/322261.322269



Related Items

The applicability of discrete performance estimation methods to VLSI design, Area-time lower-bound techniques with applications to sorting, A minimum-area circuit for \(\ell\)-selection, A class of systolic multiplier units for VLSI technology, On problem transformability in VLSI, On the VLSI complexity of some arithmetic and numerical problems, Randomization and the parallel solution of linear algebra problems, Fast and highly compact RNS multipliers, A Monte Carlo method for the parallel solution of linear systems, Communication complexity of matrix computation over finite fields, Area efficient methods to increase the reliability of combinatorial circuits, Algorithms for the Multiplication Table Problem, Area-time optimal VLSI networks for multiplying matrices, The complexity of a VLSI adder, Area-time tradeoffs for matrix multiplication and related problems in VLSI models, The area-time complexity of the greatest common divisor problem: A lower bound, The cut theorem—a tool for design of systolic algorithms, The communication complexity of several problems in matrix computation, Really Fast Syndrome-Based Hashing, A note on optimal area algorithms for upward drawings of binary trees, Semelectivity is not sufficient, Explicit bounds for primes in residue classes, Advances in the theory and practice of graph drawing, Where-oblivious is not sufficient, Unbounded hardware is equivalent to deterministic Turing machines, Area-time tradeoff for rectangular matrix multiplication in VLSI models, Area-period tradeoffs for multiplication of rectangular matrices, Optimizing area and aspect ratio in straight-line orthogonal tree drawings, Area complexity of merging, The performance of multilective VLSI algorithms