Built-in self-test quality assessment using hardware fault emulation in FPGAS

MaRDI QIDQ5478931zbMATH OpenFDO

Authors Abílio Parreira, Joao Paulo Fernandes Teixeira, Marcelino B. Santos

Publication date 14 July 2006

zbMATH Keywords

ASICBISTfault coverageFPGAHardware Fault Emulation

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Recommendations

• scientific article; zbMATH DE number 1844672
• scientific article; zbMATH DE number 1941114
• The method of parallel-sequential built-in self-testing in integrated circuits of the type sFPGAs
• scientific article; zbMATH DE number 1941184
• BIST for systems-on-a-chip

Cited in

(1)

• The method of parallel-sequential built-in self-testing in integrated circuits of the type sFPGAs

This page was built for publication: Built-in self-test quality assessment using hardware fault emulation in FPGAS

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5478931)