Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays

DOI10.1109/TC.1978.1675203MaRDI QIDQ4174638zbMATH OpenOpenAlexFDO

Authors Mabo R. Ito, R. D. Cameron

Publication date 1978

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1978.1675203

zbMATH Keywords

Binary Code TranslationCounter-Driven State MachineMicroprogrammed State MachineParallel To Serial ConversionProgrammed Logic ArrayRead-Only MemoryShift RegisterStored Logic ArrayTranslate Table

Mathematics Subject Classification ID

Theory of software (68N99) Formal languages and automata (68Q45) Theory of error-correcting codes and error-detecting codes (94B99) Circuits, networks (94C99)

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