Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays (Q4174638)
From MaRDI portal
!
This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:
scientific article; zbMATH DE number 3609583
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays |
scientific article; zbMATH DE number 3609583 |
Statements
Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays (English)
0 references
1978
0 references
Binary Code Translation
0 references
Microprogrammed State Machine
0 references
Parallel To Serial Conversion
0 references
Stored Logic Array
0 references
Translate Table
0 references
Programmed Logic Array
0 references
Shift Register
0 references
Read-Only Memory
0 references
Counter-Driven State Machine
0 references
