DCT hardware structure for sequentially presented data

DOI10.1016/S0165-1684(01)00113-XMaRDI QIDQ5958658zbMATH OpenFDO

Authors T. C. Tan, G. Bi, Y. Zeng, H. N. Tan

Publication date 3 March 2002

Published in Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S0165-1684(01)00113-X

zbMATH Keywords

bit-serial processingdiscrete cosine transform

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

Review text

This paper shows that a fast discrete cosine transform (DCT) algorithm is mapped into a hardware structure that consists of \(\log_{2} N\) modules. Such a hardware structure can be used for bit-serial word-serial or word-serial bit-parallel implementation. Compared to other methods of hardware implementation, the proposed one provides a natural interface with sequentially presented input data, achieves a high utilization of hardware, requires a low processing latency and has a modular architecture that can be extended to support different transform sizes.

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• An efficient hardware accelerator architecture for implementing fast IMDCT computation

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