Detection of Multiple Faults in Combinational Logic Networks

DOI10.1109/TC.1972.5009008MaRDI QIDQ5680043zbMATH OpenOpenAlexFDO

Authors Igal Kohavi, Zvi Kohavi

Publication date 1972

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1972.5009008

Mathematics Subject Classification ID

Cited in

(4)

• Checking experiments for sequential machines
• Deriving approximate logic circuits for TMR technique
• Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits
• Path delay and multiple stuck-at fault test design for circuits derived from irredundant systems with factorized synthesis method

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