Discrete semantics for reversible transistor network verification

DOI10.1007/978-3-032-30839-9_6MaRDI QIDQ7411925zbMATH OpenFDO

Authors Hannah Blyton

Publication date 2026

Full work available at URL https://doi.org/10.1007/978-3-032-30839-9_6

zbMATH Keywords

formal verificationreversibletheorem provingtransistor simulation

Mathematics Subject Classification ID

Other nonclassical models of computation (68Q09) Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Quantum computation (81P68)

Cites work

• A Switch-Level Model and Simulator for MOS Digital Systems
• Formal verification of floating-point hardware design. A mathematical approach
• Irreversibility and Heat Generation in the Computing Process
• The Lean 4 theorem prover and programming language

This page was built for publication: Discrete semantics for reversible transistor network verification

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q7411925)