A Switch-Level Model and Simulator for MOS Digital Systems

DOI10.1109/TC.1984.1676408MaRDI QIDQ3312162zbMATH OpenFDO

Authors Randal E. Bryant

Publication date 1984

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1984.1676408

zbMATH Keywords

MOS logic simulationswitch graphsswitch-level modelVLSI

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15)

Cited in

(9)

• An optimistic ternary simulation of gate races
• Efficient distributed simulation of acyclic systems
• Constructive polychronous systems
• Applying Light-Weight Theorem Proving to Debugging and Verifying Pointer Programs
• A two-level formal verification methodology using HOL and COSMOS
• A model for synchronous switching circuits and its theory of correctness
• Invariant and dual-invariant subspaces of k-valued networks
• On the existence of speed-independent circuits
• A theory for the derivation of combination C-mos circuit designs

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