Double-Data-Rate Computation as a Countermeasure against Fault Analysis

DOI10.1109/TC.2008.149MaRDI QIDQ4975072zbMATH OpenOpenAlexFDO

Authors P. Maistri, R. Leveugle

Publication date 8 August 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2008.149

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Recommendations

• Fault tolerant arithmetic unit using duplication and residue codes
• Cryptanalysis of two fault countermeasure schemes
• On double exponentiation for securing RSA against fault analysis
• Dual-rail transition logic: A logic style for counteracting power analysis attacks
• Double fault distinguishability in linear systems
• Differential Fault Analysis on DES Middle Rounds

Cited in

(1)

• Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA

This page was built for publication: Double-Data-Rate Computation as a Countermeasure against Fault Analysis

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4975072)